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Lm13700 Osc - Sync?
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bugbrand



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PostPosted: Thu Jan 31, 2008 4:44 pm    Post subject: Lm13700 Osc - Sync? Reply with quote  Mark this post and the followings unread

Hey, I'm working on a VCO along quite similar lines to Thomas Henry's LMVCO (in AS21C) and wondered how you'd go about adding a sync input???

My presumption would be to momentarily short the cap - you could do that with a 4016 gate but that'd be big and clunky (unless the other gates were used?). So, perhaps with a JFET?

Any pointers to schematics perhaps?

Thanks!

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frijitz



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PostPosted: Thu Jan 31, 2008 7:57 pm    Post subject: Re: Lm13700 Osc - Sync? Reply with quote  Mark this post and the followings unread

bugbrand wrote:
Hey, I'm working on a VCO along quite similar lines to Thomas Henry's LMVCO (in AS21C) and wondered how you'd go about adding a sync input???


Usually easy to put in something simple, but could you give us a bit more information on what the core is like? Tri? Saw? What kind of switch?

Very Happy

Ian
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bugbrand



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PostPosted: Fri Feb 01, 2008 3:11 am    Post subject: Reply with quote  Mark this post and the followings unread

Ah yes - info! Good point, Ian.

Ok, I'm posting up the schematic which I drew out last night - the full thing isn't tested though I've been through most of the parts on breadboard.
Its a design for a reasonably simple modulation osc - ie, I'm not too worried about perfect tracking. The Osc core is straight from the LM13700 datasheet - we then take the triangle and generate a square from it (pulse width adjustable - I didn't want to fit full PWM) and then we have a linear VC crossfade using a 2nd LM13700.

So, the point for sync would be cap C1..

Cheers!


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frijitz



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PostPosted: Fri Feb 01, 2008 6:53 am    Post subject: Reply with quote  Mark this post and the followings unread

bugbrand wrote:
Its a design for a reasonably simple modulation osc - ie, I'm not too worried about perfect tracking. The Osc core is straight from the LM13700 datasheet
Hi Bug --
I haven't worked with that exact circuit, but I can give you a couple of ideas. There are basically two ways to go about adding sync. One is to short the cap, as you asked about, and the other is to force a transition in the current reversing switch.

First you need to generate a triggering pulse. You can do this by feeding the Sync In to an RC differentiator driving a comparator. A Saw or Pulse input will then give you a big pulse out of the comparator.

To reset the cap, put a JFET plus a series resistor (22k or so) across the cap and drive its gate from the comparator through a 100k resistor.

To reset the switch, you could try using a JFET connected from +15V through a series resistor to R7. You can see a similar method, which modulates the trip point of the switch, here (scroll way down):
http://home.comcast.net/~ijfritz/sy_cir4.htm

Hope this is enough to get you started. I've used both methods, but not with your exact circuit. It usually takes a bit of adjusting to get a sync circuit to work well, since operation depends on the driving signal to some extent.

Please keep us posted on how this works for you.

Very Happy

Ian
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bugbrand



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PostPosted: Fri Feb 01, 2008 11:59 am    Post subject: Reply with quote  Mark this post and the followings unread

Thanks a lot for the ideas and details Ian! That's a real help.

I think I'll certainly look first at the JFet method - that's along the lines I was thinking about, I just needed some firming up! Definitely time to bread board some more.

I'm hoping this may work out as a nice compact module - primarily aimed at LFO modulation, but of course with possibility to be a droning osc too. I envisage a bank of two or three of them with cross modulation between them all (..it'd be a lot easier if I banana systems allowed normalisation - it'll have to be switches). Anyways, if the design moves forward well I'd really love to turn this into a proper pcb and share it around..

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intellijel



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PostPosted: Mon Aug 16, 2010 9:46 pm    Post subject: Reply with quote  Mark this post and the followings unread

Why does the JFET option require a series resistor to the gate? I have seen this in other circuits as well but I do not understand why you would need to limit the current to a fet gate.
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