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 Forum index » DIY Hardware and Software » Microcontrollers and Programmable Logic
Verilog for FPGA question
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jksuperstar



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PostPosted: Sat Oct 03, 2009 1:58 pm    Post subject: Reply with quote  Mark this post and the followings unread

Well, one thing to remember with FPGAs, is that they are built on basically RAM look-up tables. All logic is created using them. So, "logic depth" really only depends on how many inputs to that combinatorial logic there is. You can look up the architecture of the Spartan 3, and I think it has 6 inputs to each slice, with built in carry through for shift or adding, so anything with 6 inputs or less, is 1 slice,or logic element, deep. No matter what the equation. 7 - 12 would be two, maybe three, etc.
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JovianPyx



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PostPosted: Tue Oct 06, 2009 2:00 pm    Post subject: Reply with quote  Mark this post and the followings unread

I understand FPGA internal structure. My point isn't to never use combinatorial logic, rather that when combinatorial strings become longer, the inputs take longer to propogate. A solution to that is to break the logic into steps that can be done in sequence and configure a state machine to do the sequencing. The clock then determines how much combinatorial slack time you have, so you might be able to do a whole MAC or a very wide MAC or maybe only the multiply.

Just to give a real example of what I'm talking about, I'm working on a 16 voice synth where a voice is coded as a module instantiated 16 times and all run in parallel. To get an output to the DAC, each of the voice modules must contribute it's output to a mixer sum. At first, I tried a simple combinatorial adder string O0 + O1 + O2 + ... + O15 which failed the timing constraint. Simply adding parenthesis to create a binary adder tree was better, but failed the timing constraint as well. I ended up creating an accumulator and doing each add in it's own clock tick after the modules finished their computations.

Marginally long combinatorial strings can be very frustrating as they can work in the current version of a design, but then break when more logic is added and the design is forced to deal with longer routing times.

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jksuperstar



Joined: Aug 20, 2004
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PostPosted: Tue Oct 06, 2009 3:47 pm    Post subject: Reply with quote  Mark this post and the followings unread

I understand your problem, and I know you do as well, and unfortunately it's my nature to keep offering information regarding what I'm thinking, not only for your sake, but also for anyone else reading the thread. That gives me the opportunity to get feedback on what I'm thinking, too, so please don't take this thread to be on the air of a lecture, or any type of judgement.

In that light, one thing you can use in the XST synthesis tools, is Register retiming/pipelining. If you have a path of data that takes, say, 3 clock cycles to compute through (in pipeline fashion), you can enable these features, and the tool will identify the datapath/pipeline, guarantee the input and output of that pipeline to be accurate, then move logic around inside the pipeline to meet timing.

For example, for your output mixer, you could have all 16 values going into adder, then into a 3 deep registered pipeline (no logic between them). The tool could then move the the additions that are done into space that's between those registers, and also create new registers where needed, so that the final output of the pipeline was still the final sum of 16 voices you'd expect. The value of those first two layers of pipeline would be different, and may not even be the same bit width. The tool tries to make a judgement call based on whether you wanted area or performance as the priority, and will insert extra registers or anything else that's needed.

It saves you the trouble of hand-planning things (which I do believe in) to the point of killing time (which I don't). It also allows your design to be a little more architecture independent, so the tools allow the design to take more advantage of the resources available. If you ever pick up a new FPGA board down the road, and want to expand your design to 32 voices for example, the tools can help keep the RTL changes minimal.
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JovianPyx



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PostPosted: Tue Oct 06, 2009 5:35 pm    Post subject: Reply with quote  Mark this post and the followings unread

We're on the same page.

As for information for others who might read this - that's why I post too. I figure someone might read that and not have to bang his/her head against the wall the way I did.

I wasn't aware that XST would do that.

It's a "style" thing, but I like the "by hand" method because for old guys like me it helps to stave off Alzheimer's. More than that is that I am forced to plan the entire system.

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FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.
Fruit flies when you're having fun.
BTW, Do these genes make my ass look fat?
corruptio optimi pessima
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