CD4029 based sequencer skipping 0

[elmegil]

I'm working on a trigger/gate sequencer.

First rule of responses: don't tell me I ought to be using (insert your favorite programming platform), because I don't want this to be something people have to flash/program, and I don't want it to be something I have to supply programmed chips for. It's nice if you don't think that's an impediment, but some people still do and I want to include them if this thing ever gets to the "selling it from Synthcube" stage.

Design points:

Variable duty cycle output, so we can sequence triggers to gates.
Up/Down control
Ability to use it for 16 steps or 2x8 steps
CVs (gates, really) over all these controls
Clock out/clock in so you can chain several of them

Up/Down led me to the CD4029

Intent to generate variable duty cycle via AND with step gates led me to a variable duty cycle clock -- 555 for the basic clock, use the triangle buffered and run through a comparator to get the duty cycle.

Using 2 x 4051 to decode the counter into either 8 steps, or using the high bit of the clock and its inverse to alternate the two for 16 steps.

Initial problem was my clock was using an LM311 for the comparator, and only getting 0->6V, when it needed to be 10-12V for the high side.

Revised the comparator to use an LM358 (single supply config) and I'm getting a decent clock out of it.

What is weird is that from the start, when the counter was working, it was skipping steps. Counting up it would skip 0 and 8, counting down it would skip 4 and 12.

After adding a transistor buffer on the clock input, I'm no longer skipping 8 when counting up, nor am I skipping anything when I count down. But I am still skipping 0 when counting up.

So other relevant things....

the jam inputs are all grounded, as is carry in.
the load jam inputs ("PE") pin is connected both to a power on reset (cap to +V, resistor to ground) and to a diode coming from the reset input which is transistor buffered and normalled to a reset button. Pressing the reset button gets the expected result of resetting to 0 (and always has).



The schematic is something of a problem, it's actually split over multiple sheets, but the relevant bit with the 4029 is here.


I am simply not grasping why it would skip step 0. There's nothing odd about the clock as far as I can tell, for testing it's on its own power supply all alone...... Hoping someone with more CMOS experience can point to something. Speaking of which, all chips have 100nF bypass caps near their power pins.

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[elmegil]

Oh, and ignore the headers at the top; this was an experiment in how I could indicate mating headers between two boards -- controls and a little bit of support stuff is on a panel PCB, the main logic is on its own PCB. I hate the way this looks, it only made sense when I was first drawing it, and I just haven't gone back to revise it.


Overall this is going to go through a lot of serious revision (changing the switches, which also means changing to do something else instead of a 3 pole switch, they don't apparently make those in submini). But I want to get all the stupid mistakes resolved before I do that.....


And yes, I have realized I have no Run/Stop

[Grumble]

By "skipping" you mean the outputs of the 4029, or the outputs of the 4051?
I mean: where did you noticed the skipping?
Because if you say that the skipping occurs at some point at 0,8,4 and 12 it's common nominator is Q4 of the 4029, so my guess is that there is something wrong with it (bad solder, shortcut ...)

[PHOBoS]

A resistor from the base of Q4 to GND might help. I had some problems with skipping
when using a resistor that was too large and you don't have one at all. I wasn't using
the transistors as an emitter follower though, but I think it's worth a try. btw. If you use
them like this it will most likely not work with 5V gate/triggers signals.

[Grumble]

Why not use the same resistor values around Q4 as with Q? (that's the Q with the question mark

[gdavis]

Sorry I don't have time to read everything and go into detail right now, but I really don't think you should be using emitter-followers to buffer the inputs of the CMOS chips. And the diode on reset makes things even worse and seems completely superfluous. Anyway, I can explain more later if you want.

[gdavis]

OK, I took another look and your inputs are seriously flawed. There's absolutely no way this thing can be expected to work reliably.

1. As I mentioned above, you don't want to use emitter-followers for logic. The output of the emitter-follower is going to follow the input voltage but lose one diode drop through the base-emitter junction (about 0.6V). So for a high input at best you get Vin - 0.6V (reset is even worse with the extra diode). The problem is that CMOS logic really wants to be driven by Vdd and Vss for high and low respectively (as close as you can get to this). so a) your clock input needs to be very specific and b) you don't want to be giving up that diode drop.

Edit: Disregard point 2. This analysis is incorrect.
2. The base and emitter resistors of Q? and Q4 (you really should annotate your schematics before posting them for help) are forming voltage dividers in addition to the drop of the emitter follower. With the values shown, you are reducing the input by about 1/10. This is going to kill the circuits ability to operate properly, especially on the clock.

3. Your reset input is floating when there's nothing connected and the button isn't being pressed. Add a pull down before the transistor base.

I would suggest replacing the emitter followers with common emitters like Q5 and Q6. Then you know you are getting the correct voltages to the CMOS inputs regardless of the external input voltages, as long as they cleanly cross the threshold of the transistor.

I also don't see the need for R41, C16 and D3. I'm guessing you're trying to extend the reset pulse? Are you worried that your reset source is going to generate too quick of a pulse?

Edit: I just read your explanation of the reset. Not sure it's going to work reliably, might work well enough. I don't see it as critical so I'm not worried about it, but you should fix the input as explained above.

[elmegil]

[elmegil]

[elmegil]

[elmegil]

[elmegil]

a 10K pulldown on Q4 and eliminating D3 was insufficient.

I will see whether additional replies help me understand better before I go poking around with random values though....

Again: thanks very much for all the replies. I have a degree, but I was never very good with transistors (obviously ), and that degree didn't get used in any practical way for 25 or so years, so even what I did know is all pretty rusty where it hasn't been polished by actual use troubleshooting other circuits.....

[PHOBoS]

[elmegil]

so either 1) I'm not actually driving the transistor into saturation or 2) I have no goddamn idea what I'm doing with transistors and should go grow cabbages. Possibly both.

[PHOBoS]

It doesn't have anything to do with saturation but the way the transistor is configured in the circuit. this might clear things up a bit.
Growing cabbages can be fun if you like them. I once grew a Romanesco broccoli, beautiful plant and tasted good too.

[gdavis]

[elmegil]

[gdavis]

[elmegil]

[JovianPyx]

I think gdavis was referring to the use of the 40106, not that it is a slow IC. A schmitt trigger input gate works well with signals the rise or fall slowly. Non schmitt trigger gates don't like this and can generate noisy output while the input signal is changing values.

[PHOBoS]

Instead of using 2 schmitt trigger inverters, which won't really help you, use a transistor (configured the same way as
Q5, Q6 in the original schematic but with a resistor to GND) followed by 1 schmitt trigger inverter. This will give you
a wider voltage range and because of the schmitt triggers smooth transitions at a logic level. Or, as I mentioned before,
some simple comparators which have always worked great for me.

[gdavis]

[electrotech]

Hello,

If you'd like to use a simple all-discrete component circuit for the clock interfacing, I'd like to offer the attached one I came up with. It's already been suggested above and personally, I think it's all that's needed
The CMOS inverters that are being considered would still need additional voltage level translation to work with a 5V clock for example.
In my circuit, the over-voltage and polarity protection is taken care of by the zener diode.
Bipolar or unipolar clock inputs from 3V upwards are catered for.
The resistors either limit the current or act as potential dividers to enable clean switching of the transistors, there being one NPN type followed by a PNP type so that the output signal is just a 0 to 12V clock signal in phase with the input.
I should add that I haven't actually built this but it works fine in the simulator.

Regards,
Andy
EDIT : An updated circuit plus an alternative are posted further down.

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[gdavis]

Thanks for posting that up Andy, looks like a solid solution to me

[blue hell]

Ah, that looks like design Andy