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 Forum index » DIY Hardware and Software » Musical Interfaces
Gate/Trigger Sequencer help
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simon_w



Joined: Apr 16, 2011
Posts: 1
Location: UK

PostPosted: Sat Apr 16, 2011 6:02 pm    Post subject: Gate/Trigger Sequencer help Reply with quote  Mark this post and the followings unread

Hi all,
Need some help with converting the gate output of my sequencer to short pulses/triggers. The design is basically a baby 10 sequencer - i.e. a 555 timer, with a 4017 decade counter cycling through a series of gates.
I thought this would simply be a case of taking the clock impulse and the gate signal and putting them both through an AND gate.
However, there is a slight delay between the rising clock edge and one gate changing to the next. So a spike occurs at the point when the gate is still on, as the next clock signal rises.
The attached diagram should show what (i think) is going on.
Can anyone suggest a way to remove the spike? Or a better way to compare the two signals?


CLOCK_GATE.png
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Bogus Noise



Joined: Jun 03, 2009
Posts: 59
Location: Sheffield

PostPosted: Wed Aug 24, 2011 1:10 pm    Post subject: Reply with quote  Mark this post and the followings unread

I don't know if you solved this already, or put it to one side for a while, but posting this answer for the purposes of helping out other people searching for the same problem. Smile


I'm just coming to the end (hopefully) of building a similar project which had a similar problem. I found the 555 isn't the best clock oscillator to use with the AND gate method. Lots of other chips will work much better than the 555 but I used a 4011, and still get the separated gates even when you're into the audio rate range.

You will also need to use 4 AND gates, to handle the very slight delay that the 4017 imparts. This schematic designed by someone else on here works great!

http://synthforum.nl/forums/showthread.php?p=1141314#post1141314
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Mongo1



Joined: Aug 11, 2011
Posts: 411
Location: Raleigh NC

PostPosted: Wed Aug 24, 2011 1:50 pm    Post subject: Another approach Reply with quote  Mark this post and the followings unread

We used to run into this thing very often when I designed hardware for high speed digital systems.

In cases like that, the answer is generally to get a flip-flop, run the glitchy signal into the 'D', and use the inverted version of the clock to clock the flip flop. That way those spurious pulses can't make it through.

The penalty is of course that you delay the output by 1/2 clock time - but it generally works very well.

Gary
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