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 Forum index » Clavia Nord Modular » G2 Building Blocks
Clock Multiply
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iPassenger



Joined: Jan 27, 2007
Posts: 1049
Location: Sheffield, UK
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PostPosted: Thu Apr 26, 2012 1:53 pm    Post subject: Clock Multiply
Subject description: Takes pulse signal and creates a multiple faster pulse
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I was wondering how hardware modular modules did this and figured you could use the zero count to extract the frequency of a pulse (requires two consecutive pulses to settle on a frequency), then apply this signal to an osc or lfo control input and offset the default frequency of the osc or lfo to a multiple of the default.

I needed to resync the lfo to keep the multiples in line with clock pulse but perhaps there is another way to do this to allow odd multiples like 1.5 etc..

Anyway the important bit is in red.

Smile


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varice



Joined: Dec 29, 2004
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Location: Northeastern shore of Toledo Bend
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PostPosted: Mon May 07, 2012 12:22 am    Post subject: Reply with quote  Mark this post and the followings unread

In this topic:

http://electro-music.com/forum/topic-53308.html

iPassenger wrote:
…I was hoping actually that you might have a better way of doing the clock multiply patch.


Well, if you want to use only a single clock pulse or trigger as a source (instead of using the ClkGen 1/16 and 1/96 outputs along with clock dividers), then I can’t think of a much better way to derive multiples of that clock than what you did with this patch. Using the Zero Crossing Counter module to get a control signal relative to the clock rate is a good idea (that’s what I probably should have used in my Clock Gate PW patch instead of an EG).

BTW, (ref: the tap tempo example in the ZeroCnt module help file, the LFO rate is .64Hz) the proper LFO rate settings for your patch would be: x2 = 1.28Hz, x3 = 1.92Hz, x4 = 2.56Hz. And x1.5 = 0.96Hz Wink

But, as you have probably noticed, the ZeroCnt module does not work well from a cold start. Between the start and the second clock pulse, it will generate an erroneous signal. One way around this would be to always clock the ZeroCnt module and add an on/off switch and logic to reset the LFOs and enable the clock pulses to the other modules.

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iPassenger



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PostPosted: Mon May 07, 2012 6:05 am    Post subject: Reply with quote  Mark this post and the followings unread

varice wrote:
In this topic:

BTW, (ref: the tap tempo example in the ZeroCnt module help file, the LFO rate is .64Hz) the proper LFO rate settings for your patch would be: x2 = 1.28Hz, x3 = 1.92Hz, x4 = 2.56Hz. And x1.5 = 0.96Hz Wink

But, as you have probably noticed, the ZeroCnt module does not work well from a cold start. Between the start and the second clock pulse, it will generate an erroneous signal. One way around this would be to always clock the ZeroCnt module and add an on/off switch and logic to reset the LFOs and enable the clock pulses to the other modules.


haha of course, i've got x2, x4 and x8.. doh! ahh well.

hmmm.. yeah some kind of control method to prevent it spitting that chaotic bit at the start.

EDIT: Thanks for giving it a look. Smile

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varice



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PostPosted: Mon May 07, 2012 5:57 pm    Post subject: Reply with quote  Mark this post and the followings unread

iPassenger wrote:
...Thanks for giving it a look. Smile

Your welcome Exclamation

Ah, OK, now I see how you are using this idea in your “Jebus Slice2” patch. Cool

Because of the cold start error of the ZeroCnt module, maybe you should go in a different direction, a Clock Divider instead. Hit the ZeroCnt module with the fastest clock that you will use in a patch (or even overclock it) and then set the modulated LFOs to slower rates to derive clock divisions. The faster that you clock the ZeroCnt module, the less time it will output a bogus signal at startup.

Thanks for posting this Clock Multiplier patch. The ZeroCnt module seems to be a better way (except for the cold start error) to get a control signal relative to clock rate than the way I used an EG module in my Clock Gate PW patch. But I have reduced the effect of that error by overclocking the ZeroCnt module input with the ClkGen 1/96 output (6 times the rate of the 1/16 output). I’m still working on a linear method to control the clock PW using this method though. thinking I just need to pound that nonlinear duty cycle control response into submission.

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