Shift registers as Johnson counters and 4094 serial out

[okelk]

I've been playing with 4094 shift registers configured as Johnson counters to get odd divisions with equal pulse width. (parallel output > inverter > data input).

There are some things I didn't understand so far.
What is the difference between the 8th parallel bit (QP7 in my datasheet) And the serial output QS?

Also what is QS2 good for?

[Steveg]

Hi okelk,

I'm looking at the intersil data sheet: http://www.intersil.com/content/dam/Intersil/documents/cd40/cd4094bms.pdf

The 4094 is a pretty complex shift register with a lot going on under the hood.
Intersil QS (pin 9) is the same as the 8th stage of the shift register and could be used to chain multiple 4094s together.
Intersil Q'S (pin 10) is the same as QS but is made available on the falling edge of the clock pulse in case your timing needs that.
To get Intersil Q8 (pin 11) to show the same as QS you have to move the current state of the shift register into the latch by triggering STROBE (pin 1) and set OUTPUT ENABLE (pin 15) high.

In it's original application the chip would be clocked by the serial data clock into the shift register without disturbing the parallel out while using QS or Q'S to chain registers.
When the last bit was clocked in STROBE would be set high to latch the contents. This made the shift register available to immediately start clocking the next serial word without any pause.
At its leisure the CPU could activate OUTPUT ENABLE to grab the contents of the latch. As long as the CPU guaranteed to grab the data before the next word had been clocked in the two parts could run at different clock rates without loss of data.

[okelk]

Thanks Steveg!

I read the datasheet before, but thanks to your explanation I finally understand it.

For my application ( and probably for most lunettta stuff ) I just connected strobe and output enable to VDD

[Steveg]

I'm pretty sure that will work!