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 Forum index » DIY Hardware and Software
implementing sync
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BOB-SNARE



Joined: Sep 26, 2008
Posts: 30
Location: Australia
PostPosted: Thu Oct 30, 2008 6:10 pm    Post subject: Reply with quote  Mark this post and the followings unread
frijitz wrote:
bugbrand wrote:
Sounds similar to what I suggested for an alternate XR2206 sync:
http://electro-music.com/forum/viewtopic.php?highlight=sync&t=28182

I'm having trouble understanding that circuit. Aren't T1 and D2 biased on all the time? I don't see how the FET gets pinched off.


Isn't T1 an emitter follower?
Assuming a single-sided supply (+V) to the XR2206 (as in the XRVCO
schematics), the timing capacitors sit around V+/2.
When there's no sync pulse, Vg = 0V-Vdiode So Vgs should be -6V (less than Vp and pinched-off).
With a +V sync pulse, Vg should rise to +V-Vbe-Vdiode and Vgs is in the saturation region and conducting, shorting out the timing caps.
Does that sound correct?
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frijitz



Joined: May 04, 2007
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PostPosted: Thu Oct 30, 2008 10:01 pm    Post subject: Reply with quote  Mark this post and the followings unread
BOB-SNARE wrote:
Assuming a single-sided supply (+V) to the XR2206 (as in the XRVCO schematics), the timing capacitors sit around V+/2.
When there's no sync pulse, Vg = 0V-Vdiode So Vgs should be -6V (less than Vp and pinched-off).
With a +V sync pulse, Vg should rise to +V-Vbe-Vdiode and Vgs is in the saturation region and conducting, shorting out the timing caps.
Does that sound correct?

Ah, thanks. I didn't understand that the cap voltage is always close to V+/2.

Very Happy

Ian
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bugbrand



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PostPosted: Fri Oct 31, 2008 12:55 am    Post subject: Reply with quote  Mark this post and the followings unread
Hey Ian - your reply got me puzzled/worried -- I can't pretend to know much about JFets and had figured things in an empirical manner!
Thanks for the explanation Bob - I should look into the details of that to get a better understanding of the workings.
Cheers both.
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Luka



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PostPosted: Fri Oct 31, 2008 2:07 am    Post subject: Reply with quote  Mark this post and the followings unread
is there any good references for learning jfet/mosfet tricks?

i have asked a few people and it seems like knowledge of the gods only passed on by sacrificial offerings Smile
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BOB-SNARE



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PostPosted: Fri Oct 31, 2008 4:22 am    Post subject: Reply with quote  Mark this post and the followings unread
This is a cute little flash website for n-channel jfet
http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/jfet.html
and mosfet
http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html
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Luka



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PostPosted: Fri Oct 31, 2008 4:52 am    Post subject: Reply with quote  Mark this post and the followings unread
cheers bob
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Luka



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PostPosted: Wed Feb 11, 2009 1:50 pm    Post subject: Reply with quote  Mark this post and the followings unread
ok after reading a few things and checking out some other examples of sync here is my first implementation of syncing this circuit. i have not bredboarded it yet the parts are on route from futurlec as we speak (so might be another month Smile )



im wondering if i have to condition the incoming sync signal.
should i send it to a comperator or buffer and then feed that into the jfet


any comments would be awesome

qlfo-sync.jpg
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digisound80-23 quadlfo w/ sync input mod (draft1)
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qlfo-sync.jpg

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problemchild
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cthulu



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PostPosted: Wed Feb 11, 2009 3:23 pm    Post subject: Reply with quote  Mark this post and the followings unread
I'm not good with trannies really, but I think it would want you to add a resistor to ground (or V+???)...
A DC path between the gate and the cap.
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BOB-SNARE



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PostPosted: Wed Feb 11, 2009 5:33 pm    Post subject: Reply with quote  Mark this post and the followings unread
Luka wrote:
ok after reading a few things and checking out some other examples of sync here is my first implementation of syncing this circuit. i have not bredboarded it yet the parts are on route from futurlec as we speak (so might be another month Smile )



im wondering if i have to condition the incoming sync signal.
should i send it to a comperator or buffer and then feed that into the jfet


any comments would be awesome


Apart from controlling Vgs on the nFET properly, Vgs < Vp (pinchoff voltage) to turn off the FET. Look at the quoted examples
http://electro-music.com/forum/viewtopic.php?highlight=sync&t=28182

The cap shorting method doesn't reset up/down direction.
The comparator (bottom right op-amp) has hysteresis, so when the cap is shorted out, the integrating op-amp (bottom left) output goes to 0V, which is effectively mid-level for a bi-polar output and the state of the comparator will remain unchanged.


Cheers
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widdly



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PostPosted: Wed Feb 11, 2009 6:47 pm    Post subject: Reply with quote  Mark this post and the followings unread
The electric druid LFO has a sync input (along with loads of other features).

http://www.electricdruid.net/forums.html?page=projects.lfo9
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Luka



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PostPosted: Wed Feb 11, 2009 10:31 pm    Post subject: Reply with quote  Mark this post and the followings unread
that looks great widdly but i dont have a PIC burner and im kinda keen to nut out this problem on the schem i have at the moment.

thanks bob-s
ill try tom's example

it looks pretty good
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