Upcoming Chips: 144x Stackprocessor Arrays

[kybertech]

I have found some interesting chips. The company behind it are GreenArray Inc.
( http://www.greenarraychips.com/ )

You may have heard of Chuck Moore. This guy basically is the godfather of FORTH.
His webpage: http://colorforth.com/
there is some information about his new 'colorforth' among other things.
After failure of a similar project with 40 processors on a chip (SEAForth) the new chips with 144 processors are said to be in production and you can preorder samples and boards. The Boards are fairly expensive considering they do not provide you with any extra peripherals. They are just 2 of the chips with some sram and flash and 2 serial ports.

However the potential processing power in these things makes them interesting...
They run at 700 mhz with 1 cycle instructions (there are only 33 of them though) which would give you 201.600mips on the board. So something like a "Nord Modular on Steroids", Resynthesis, FM with arbitrary operator count or something like that would be possible with this.


There are some downsides though:
There is no C compiler but you can do highlevel programming in FORTH and if you want to use memory on a selfmade board you have to write your own memory controller and the chips come in a BGA package...


I'm thinking of preordering a board nevertheless, let me know if anyone is interested, they give a discount at 10 pieces

[jksuperstar]

These are cool, I remember reading about the F18A some time ago, and even designed my own stack based 32 instruction processor. They have serious limitations when it comes to memory though. At least, when you have a few hundred on a single chip.

I got very interested in this stuff, until Nvidia announced their CUDA project several years ago. At those prices, and that performance for a fully parallelized processing unit, it became easier to learn programming, rather than continue hardware development. However, I still don't own a CUDA compliant video card yet, as I got side tracked by other DSPs.

[kybertech]

[mhelin]

If you want to do something like that now go for the XMOS XCore stuff. Like XS1-G4 on XMOS's XC-1A kit:

http://www.xmos.com/products/development-kits/xc-1a-development-kit

There are only four cores though, but each have 8 threads processing simultaneus events in total of 32 threads. There isn't either too much SRAM on chip but it would be quite easy to interface some serial chip like proposed above let a single thread handle the job.

[jksuperstar]

No real info. I didn't do any documentation, and just hobbled an instruction decoder and math pipeline together with a handful of registers and a stack. but I wanted to add a memory interface to the bottom of the stack, so the stack could be as large as your memory was. Being only 5 bits to decode, it was fairly fast, and that also meant 4-6 instructions could be read at once into the pipe.

It did make me realize that these processors aren't completely unique. The old SPARC, followed by the ARM processors, have an architecture that 1/2 the RISC registers gets swapped depending on the mode (system, IRQ slow, FF IRQ, user, etc).

[kybertech]

[jksuperstar]

I just found the switching of register sets as avoiding the need to dump them off to a stack during a context switch. Which is the same claim that stack based processors make: you don't need to waste time pushing registers to an external stack during a context switch. Because the stack as already built-in.

Also, my thought of adding a hardware memory interface at the bottom of the stack was to allow for any sized memory. The CPU could only jump a small amount, or address a limited size of the stack, but the total space available was much larger. However, since I dropped development of it, I never really profiled any programs to see if that idea would help in any way