Beginner Verilog Question

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

I'm writing some basic verilog for what is essentially an asynchronous buffer, but I'm running into a fundamental problem.

I have a "full" flag that I would like to go high when data is clocked in, and low when data is clocked out.

If I set it up like this:

JovianPyx · Posted: Sun Apr 12, 2009 9:05 pm Post subject:

The reason for the error is that you are writing to register FULL from two different always blocks. Combine all of the logic into one always block to make this work. The two always blocks *look* like they make sense, but from a Verilog standpoint, they don't know about each other.

something like:

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

Thank you for the response.

I spent a couple more hours on this today, and have some more points/questions.

According to the Verilog book that I have, it is valid to have:

JovianPyx · Posted: Sun Apr 12, 2009 10:10 pm Post subject:

"assign" cannot be used with a register object type, only with a wire object type. At least that's never worked for me.

If you are attempting to set a register's contents to different values under different logic conditions, then you must do so within the same always block.

-- note that my experience is with Xilinx FPGA parts... when I have tried to set a register value within more than one always block, I have received the error that you received. Combining the logic into a single always block has always fixed the problem.

It may not produce elegant looking code, however, if the code works, then I consider it correct from a pragmatic standpoint.

Are you sure that you can't do this based on an always block conditioned only by the system clock? It seems to me that you should be able to do that. What's odd about what you wrote is the sensed condition of ADDR. If you use the system clock to capture the state of ADDR as OLD_ADDR and compare OLD_ADDR to ADDR you can sense when ADDR changes and use that signal to do whatever else you want to do. But I am accustomed to using an FPGA which is an ocean of fabric compared to a CPLD.

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

JovianPyx · Posted: Sun Apr 12, 2009 10:22 pm Post subject:

I'm curious - you said that you were able to construct the logic based on an always block sensing only posedge of the system clock, but that it was complex - did that logic simulate correctly?

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

The last block of code I posted was meant to combine rising edge detection (of CLKIN) with output reading detection (based on ADDR changing). In simulation it shows up as a monostable multivibrator triggered on rising edges of CLKIN. That is, when CLKIN goes from low to high, FULL goes from low to high to low. I only want it to reset when the signal on the ADDR pins changes, but it resets on its own.

JovianPyx · Posted: Sun Apr 12, 2009 10:56 pm Post subject:

Have you tried to construct the logic based on:

jksuperstar · Posted: Mon Apr 13, 2009 11:08 am Post subject:

For verilog, to use a clock along with an asynchronous low-assertion reset, it's coded as follows:

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

I'm essentially trying to make a 16x1 asynchronous FIFO. I don't know if that's the right number order, but it's supposed to be 16 bits wide, 1 stage deep. I can run 4x CD74HC40105, but that seems like a lot of waste at 16x16.

The buffer fits in like this:

uP #1 -> buffer -> uP #2

Where the two microprocessors have independent (and separately variable, but that's another story) clocks.

Altera has a drop-in "FIFO" block, of course, but it doesn't allow for less than 4 stages. 4x16 = 64, which is already every macrocell in a $2 CPLD.

jksuperstar · Posted: Mon Apr 13, 2009 8:21 pm Post subject:

I assume you have two different microcontrollers, each with an asynchronous bus? Hence, without a clock, you're hoping to have an asynchronous "FIFO" (honestly, I've never seen a 1-deep FIFO, though the term does seem to fit!).

If my assumptions are right, in most hardware and software terms, you're looking for a mailbox register, with hardware spin-lock. One uP writes the mailbox, and that in turn sends an IRQ, or other, to the 2nd uP. Meanwhile, the 1st uP can't write again until the mailbox has been read/cleared.

In an FPGA, the 4 deep FIFO could work just fine for you, in fact it would allow for longer messages to be passed before being locked out. There is no increase in latency, as a FIFO tracks where each data is written, so the read can happen right away. And it won't cost much, since each Logic Cell that has 1 lookup table, and 1 register, and it can turn the look up table into a "memory" to be used for a FIFO). But, you're in a CPLD...

The real dilemma in asynchronous design is in race conditions. That one in a billion chance of the timing happening just right, to foil your logic. Which is why you don't want a latch. It makes that case happen much more often. And at MHz designs, the failure can happen more often than you think!

All said, a Set-Reset flop might be ok, as long as you make sure you read that the FIFO is not full, THEN do the next write (in the 1st uP). If you can, avoid doing a check on address change, and just have the mailbox set to either a single register, or an empty range of registers (less bits to decode).

So:

urbanscallywag · Joined: Nov 30, 2007 Posts: 317 Location: sometimes

Asynchronous designs in CPLD/FPGA are just asking for trouble, especially for beginners.

I think what you should be building is a dual-clock FIFO, though this is more commonly done in FPGA where you have block RAM to work with.

Cross clock domain circuits are not easy.