Author |
Message |
iPassenger
Joined: Jan 27, 2007 Posts: 1068 Location: Sheffield, UK
Audio files: 5
G2 patch files: 78
|
|
Back to top
|
|
|
varice
Joined: Dec 29, 2004 Posts: 961 Location: Northeastern shore of Toledo Bend
Audio files: 29
G2 patch files: 54
|
Posted: Mon May 07, 2012 12:22 am Post subject:
|
|
|
In this topic:
http://electro-music.com/forum/topic-53308.html
iPassenger wrote: | …I was hoping actually that you might have a better way of doing the clock multiply patch. |
Well, if you want to use only a single clock pulse or trigger as a source (instead of using the ClkGen 1/16 and 1/96 outputs along with clock dividers), then I can’t think of a much better way to derive multiples of that clock than what you did with this patch. Using the Zero Crossing Counter module to get a control signal relative to the clock rate is a good idea (that’s what I probably should have used in my Clock Gate PW patch instead of an EG).
BTW, (ref: the tap tempo example in the ZeroCnt module help file, the LFO rate is .64Hz) the proper LFO rate settings for your patch would be: x2 = 1.28Hz, x3 = 1.92Hz, x4 = 2.56Hz. And x1.5 = 0.96Hz
But, as you have probably noticed, the ZeroCnt module does not work well from a cold start. Between the start and the second clock pulse, it will generate an erroneous signal. One way around this would be to always clock the ZeroCnt module and add an on/off switch and logic to reset the LFOs and enable the clock pulses to the other modules. _________________ varice |
|
Back to top
|
|
|
iPassenger
Joined: Jan 27, 2007 Posts: 1068 Location: Sheffield, UK
Audio files: 5
G2 patch files: 78
|
Posted: Mon May 07, 2012 6:05 am Post subject:
|
|
|
varice wrote: | In this topic:
BTW, (ref: the tap tempo example in the ZeroCnt module help file, the LFO rate is .64Hz) the proper LFO rate settings for your patch would be: x2 = 1.28Hz, x3 = 1.92Hz, x4 = 2.56Hz. And x1.5 = 0.96Hz
But, as you have probably noticed, the ZeroCnt module does not work well from a cold start. Between the start and the second clock pulse, it will generate an erroneous signal. One way around this would be to always clock the ZeroCnt module and add an on/off switch and logic to reset the LFOs and enable the clock pulses to the other modules. |
haha of course, i've got x2, x4 and x8.. doh! ahh well.
hmmm.. yeah some kind of control method to prevent it spitting that chaotic bit at the start.
EDIT: Thanks for giving it a look. _________________ iP (Ross)
- http://ipassenger.bandcamp.com
- http://soundcloud.com/ipassenger |
|
Back to top
|
|
|
varice
Joined: Dec 29, 2004 Posts: 961 Location: Northeastern shore of Toledo Bend
Audio files: 29
G2 patch files: 54
|
Posted: Mon May 07, 2012 5:57 pm Post subject:
|
|
|
iPassenger wrote: | ...Thanks for giving it a look. |
Your welcome
Ah, OK, now I see how you are using this idea in your “Jebus Slice2” patch.
Because of the cold start error of the ZeroCnt module, maybe you should go in a different direction, a Clock Divider instead. Hit the ZeroCnt module with the fastest clock that you will use in a patch (or even overclock it) and then set the modulated LFOs to slower rates to derive clock divisions. The faster that you clock the ZeroCnt module, the less time it will output a bogus signal at startup.
Thanks for posting this Clock Multiplier patch. The ZeroCnt module seems to be a better way (except for the cold start error) to get a control signal relative to clock rate than the way I used an EG module in my Clock Gate PW patch. But I have reduced the effect of that error by overclocking the ZeroCnt module input with the ClkGen 1/96 output (6 times the rate of the 1/16 output). I’m still working on a linear method to control the clock PW using this method though. I just need to pound that nonlinear duty cycle control response into submission. _________________ varice |
|
Back to top
|
|
|
|