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Lorenzo
Joined: Nov 09, 2008 Posts: 375 Location: Trieste - Italy
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Posted: Mon May 17, 2010 3:16 am Post subject:
6 oscillators... can you help me? Subject description: "soft synch" |
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hi,
it is a long story... but...
I build 6 oscillators using a 40106.
The problem is:
sweeping a pot of an oscillator it interfers the pitch of other ones!
maybe I made a mistake but I think my schematic is like that:
LINK
maybe it happens because it is powered by tha same power supply.
I try building some osc using few 555... if I use different batteries I have no problems, but if I attatched all the +5v power toghether... and grounds to - pole, I have the same problem:
when I sweep a pot it change the pitch of the other oscillator!
do I made a mystake?
How can I do?
I don't want to use 6 different power suply! _________________ Yes!
Oh Yeah!
Wow! Last edited by Lorenzo on Tue May 18, 2010 6:25 am; edited 2 times in total |
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Rykhaard
Joined: Sep 02, 2007 Posts: 1290 Location: Canada
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Posted: Mon May 17, 2010 4:49 am Post subject:
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I have read a couple of times, that multiple clocks built on a single CD40106, can cause 1 or more of them, to interact with the other ones on the same chip.
A couple of things that you could try:
- add a 0.1uF capacitor directly to pin 14 of the chip, with the other end to Ground
- add a 1uF cap. directly to pin 14 as well, with it's negative end to Ground
or
- try using 2 x 40106 chips, with 3 oscillators on each of them. (1 on 1 side of the chip and 2 on the other side, with a space between them. Use the remaining inverters from each chip as output buffers for each of the clocks.
Perhaps, either of those ideas may help. |
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Lorenzo
Joined: Nov 09, 2008 Posts: 375 Location: Trieste - Italy
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Posted: Mon May 17, 2010 5:44 am Post subject:
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Rykhaard wrote: |
Perhaps, either of those ideas may help. |
Thanks
Ok... I will try both ways! _________________ Yes!
Oh Yeah!
Wow! |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon May 17, 2010 10:44 am Post subject:
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What you describe is called "soft synch".
Bipolar 555 timers are crap for audio oscillators because they "crowbar" (basically, short) the supply every time pin 3 switches state. The CMOS version - 7555 - doesn't do this and is a drop in replacement for bipolar 555.
This effect is documented for the PAiA FatMan.
The 40106 is a more difficult problem. As Rick suggested, the caps might help, however, I'd bet that they reduce it and don't eliminate it. Even with 3 oscillators per IC, you might still have this problem, though again reduced. This effect happens because the inverters all share the same internal supply lines which are eensy weensy teensy "wires" which have some resistance.
Another possible solution (or improvement) might be to use smaller timing caps with larger timing resistors; such as 10x smaller caps with 10x larger resistors This would keep the frequency range the same, but would reduce by 10x the amount of current that the gate has to sink/source when it changes state - which is what is causing this.
Also, your pot should have a series fixed resistance, if not, this will allow even more current as the frequency is increased - again, 10x smaller caps with 10x larger resistors should help.
I think that Rick's suggestions along with mine (smaller caps, larger resistors) may be the ticket, but I really don't know what level of soft synch is acceptable to you.
You might also consider trying out the CMOS 7555 timer IC instead of the bipolar 555 timer.
An alternative if you really want to use 555 (like if you have a boatload of them) is to solve the problem the way Scott Lee of PAiA did with the FatMan. Instead of putting the power rails directly on the chip, you pass the positive supply through an LED to pin 8 and then put a 100uF cap from pin 8 to ground. This will eliminate the majority of the effect. Note that the LED will not light up, it is the electrical characteristics of the diode that we're after. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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Lorenzo
Joined: Nov 09, 2008 Posts: 375 Location: Trieste - Italy
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Posted: Mon May 17, 2010 12:19 pm Post subject:
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JovianPyx wrote: | What you describe is called "soft synch". |
Oh my gosh it has a name!!
Code: |
10x smaller caps with should help. |
I will try this way... I forgot to say you that I replaced resistors with pots, in my 40106 oscillators... anyway I will link to it "10x larger resistors"
Code: | You might also consider trying out the CMOS 7555 timer IC instead of the bipolar 555 timer.
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It sounds good, but I already buoght some 555 and some 40106...
first of all I will try with those...
Quote: | An alternative if you really want to use 555 (like if you have a boatload of them) is to solve the problem the way Scott Lee of PAiA did with the FatMan. |
Thank you very much... I think I have many solutions to be tested _________________ Yes!
Oh Yeah!
Wow! |
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Rykhaard
Joined: Sep 02, 2007 Posts: 1290 Location: Canada
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Posted: Mon May 17, 2010 4:49 pm Post subject:
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Lorenzo - for the pots, to control speed for your 40106 oscillators: I use a 1 Meg pot, with a 1K resistor right after it, for a resistance range from 1,000 ohms, to 1,001,000 ohms.
The capacitor sizes that I am using are between 2.2nF and 150nF, for the 40106 oscillators. (As well as the 4023 oscillators.)
I also have 0.1uF caps at the power supply pins to both chips.
I AM having some 'cross talk' between the clocks in my system, but that also COULD be, because I am not using any shielded cable for anything in my module. There could be clock signals resonating between the wires.
If you can keep your audio wires as short as possible, and use a grounded signal wire (grounded at one end), that COULD possibly help to elimate some cross talk for you.
As to the 'soft sync' within the chips, I would follow Jovian's suggestions.
Good luck with it! If you have more questions - ask away. |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon May 17, 2010 5:42 pm Post subject:
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On a point of information Rick, where in the frequency range is the problem worst? I suspect it's at the high end... Is it?
One could also experiment with two oscillators - one sort of low to mid freq and fixed, and the other you would push as high as it can go before it messes with the low one. Then turn it all off and measure the resistance of the pot and fixed resistor on the higher freq osc - this will tell you the lowest resistance you can use. You could then change the fixed resistor to that value and quite likely get your optimum performance and being able to twizzle the knobs without worrying about soft synch - cuz it won't happen. Yes it will lower the top frequency, but if the top freq is too low - just change to a smaller cap to fix it. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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Lorenzo
Joined: Nov 09, 2008 Posts: 375 Location: Trieste - Italy
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Posted: Fri May 21, 2010 7:25 am Post subject:
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H!
I'm very happy!!!
I use 7555 finally!
At the moment 3 of them run together (5V power supplyed) and other 2 use a second power supply of 4.5V
I have to use 2 different power supply but I haven't soft synch!!!
If I use 9v there are some problems...
I have to do more experiment to determinate the picth of the oscillators, and I try to connect all 7555 to the same power supply.
I use only 5 osc... and I use it like external clocks to controll some semplers from a ROM ( this is the thread ) _________________ Yes!
Oh Yeah!
Wow! |
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