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DIY Top Octave Generator
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richardc64



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PostPosted: Tue Oct 07, 2008 11:48 am    Post subject: Reply with quote  Mark this post and the followings unread

If existing CPLDs aren't dense enough for all 12 top octave notes, how about a set of, say, 3 chips, each covering 4 notes? Setting aside the top-octave obstacle, how about binary counters denser than the standard CMOS line, such as two independent 6-bit counters in a package?

And to whomever is bold (or crazed,) enough to attempt any of these schemes, please choose a package that doesn't need a $40 adapter to make it fit a .1"x.1" grid perfboard.

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urbanscallywag



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PostPosted: Tue Oct 07, 2008 12:39 pm    Post subject: Reply with quote  Mark this post and the followings unread

Whoever does the project should probably have PCBs made since you won't find a DIP CPLD.

I would be shocked if it didn't fit in the smallest CPLD available.
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Uncle Krunkus
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PostPosted: Tue Oct 07, 2008 2:02 pm    Post subject: Reply with quote  Mark this post and the followings unread

I'd much prefer to build it out of a dozen CMOS chips! Laughing
Why is that automatically not as good as a 50240?
It'd be a lot more fun. Shocked Laughing

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blue hell
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PostPosted: Tue Oct 07, 2008 3:59 pm    Post subject: Reply with quote  Mark this post and the followings unread

It's just as good and even better in some aspects to build it from CMOS. It's a bit odd to do it that way in these times, but you'll learn good stuff from doing it, and soldering is a pretty relaxing thing to do.
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also .. could someone please turn down the thermostat a bit.
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urbanscallywag



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PostPosted: Tue Oct 07, 2008 4:21 pm    Post subject: Reply with quote  Mark this post and the followings unread

Too big, too power hungry, too much margin for error, too much soldering.

I understand analog synths, but CMOS (used purely digitally) over programmable logic? Razz
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blue hell
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PostPosted: Tue Oct 07, 2008 4:30 pm    Post subject: Reply with quote  Mark this post and the followings unread

And where soldering is relaxing, programming fucks you up Shocked
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Jan
also .. could someone please turn down the thermostat a bit.
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urbanscallywag



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PostPosted: Tue Oct 07, 2008 4:33 pm    Post subject: Reply with quote  Mark this post and the followings unread

Ah, now I see. But I don't understand. Wink
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blue hell
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PostPosted: Tue Oct 07, 2008 4:52 pm    Post subject: Reply with quote  Mark this post and the followings unread

It is ok to not understand, trust me, I have experience in that.

Of course it's madness to build the thing with CMOS, but well, people just did it 20 years ago, so why not now, as an educational exercise ... as long as it's not driven by digi-fear Wink

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Jan
also .. could someone please turn down the thermostat a bit.
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BOB-SNARE



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PostPosted: Tue Oct 07, 2008 5:17 pm    Post subject: Reply with quote  Mark this post and the followings unread

There's definitely some logic optimisation, that can be done to avoid 12 separate 9-bit counters. An interval of a 5th up is 1.5x the frequency.
e.g. for a 9-bit counter (@1MHz) a D is 426 cycles, and an A is 284 cycles
426 = 1.5*284

I'm just downloading the Xilinx webpack, and I can test out a simple design and see if it fits in a cheap 5V XC9572 CPLD. These come in PLCC packages (for those that fear surface mount).
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urbanscallywag



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PostPosted: Tue Oct 07, 2008 5:42 pm    Post subject: Reply with quote  Mark this post and the followings unread

Yeah, you should be able to do it without any programming at all now that I think about it. Just schematic capture.
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Uncle Krunkus
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PostPosted: Tue Oct 07, 2008 10:41 pm    Post subject: Reply with quote  Mark this post and the followings unread

Blue Hell wrote:
It is ok to not understand, trust me, I have experience in that.

Of course it's madness to build the thing with CMOS, but well, people just did it 20 years ago, so why not now, as an educational exercise ... as long as it's not driven by digi-fear Wink


It's not so much a case of fear as of exasperation. I don't care what anyone says, FPGAs, PICs, ATMELs etc. are just not user friendly. Unless you do that kind of thing everyday, they're just a big pain in the arse. I really wanted to get into them, I invested time, money and effort in sorting out a programmer, learning about PIC basic, building a test bed etc. etc. and then the world moves on, and the 16F84A and it's kind go out of fashion and everybody moves on. Programmer,.....now useless. PIC basic,......irrelevant. My interest,.......drained. At least CMOS still works the way it did twenty years ago.

People then start saying, "oh but it's so much easier than it was then!" So you try to make the effort to look into how it's done now.
Q: Which chip do you think I should use?
A: Have a look at this link
Q: What kind of programmer do people use now?
A: Have a look at this link
Q: How do you write the program?
A: Have a look at this link

So, if anybody's wondering why there are heaps of otherwise intelligent people out there who would rather solder up 20 chips than touch an FPGA with a bargepole.

A: Have a look at this link! Laughing

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Rykhaard



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PostPosted: Tue Oct 07, 2008 10:48 pm    Post subject: Reply with quote  Mark this post and the followings unread

Uncle Krunkus wrote:

So, if anybody's wondering why there are heaps of otherwise intelligent people out there who would rather solder up 20 chips than touch an FPGA with a bargepole.

A: Have a look at this link! Laughing


I'm with Unc. on this one. Wink I've programmed in various versions of Basic since 1982 and taught myself C++ for a few weeks, a few years ago and understood various 8 bit assemblers that I studied on my own, in the 90's but ......

I me too, would much rather stick with the CMOS. Smile (Never touched that dang ol' RTL, DTL or TTL schtuff. Jus' good ol' 'n newer CMOS. Very Happy Wink

So what if my new sequencer board I designed, came out to 6"x8". It wore still much easier to me, soldering all the chip sockets on, than learning a new language. Smile For me - chips are just that much more immediate. Smile
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Coriolis



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PostPosted: Wed Oct 08, 2008 12:04 am    Post subject: Reply with quote  Mark this post and the followings unread

Just to flog that ol' dead horse again:

IT'S DIY, RIGHT? Wink

No doubt, from a commercial, parts-count, man-hours-to-solder, board-size, etc, perspective - CMOS isn't feasible.

No doubt, from a limited-time-for-hobby, choosing-between-soldering-or-programming-and-I-already-spend-my-workday-on-a-pc, kind of perspective - learning to program just isn't feasible... Razz

How about the uC guys do a version of this, and the CMOS-guys do theirs?
Could be fun!
Besides, the whole sdiy community seems to get terribly teary-eyed over the demise of the TOG's about ten times a year, so why not make it happen?

Of course I'll be watching from the side, being neither a programmer or cmos whiz... Embarassed Laughing Rolling Eyes

Erm..carry on!

C

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Uncle Krunkus
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PostPosted: Wed Oct 08, 2008 12:22 am    Post subject: Reply with quote  Mark this post and the followings unread

Great attitude Coriolis! Very Happy
We could all gain from what can be learned here.
Believe me, I'd love to get into programming chips again. If it didn't cost me half of my spare time, half of my spare cash, and half of my spare brain cells, I'd be there in a flash! Laughing

BTW One of the secret (not so secret now Embarassed ) reasons for me wanting to do it with CMOS is that I'd like access to all those spare bits floating around! Very Happy Dirty R/2R networks take up even more board space, and cost nothing! Yeah!!

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frijitz



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PostPosted: Wed Oct 08, 2008 6:58 am    Post subject: Reply with quote  Mark this post and the followings unread

BOB-SNARE wrote:
There's definitely some logic optimisation, that can be done to avoid 12 separate 9-bit counters. An interval of a 5th up is 1.5x the frequency.


In the tempered scale the ratio for a fifth is 2^(7/12) = 1.498. So at 1 kHz this would be 2 beats per second compared to the ratio of 1.5. Not too bad. But none of the other intervals are even that close.

Very Happy

Ian
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urbanscallywag



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PostPosted: Wed Oct 08, 2008 9:25 am    Post subject: Reply with quote  Mark this post and the followings unread

Uncle Krunkus wrote:
BTW One of the secret (not so secret now Embarassed ) reasons for me wanting to do it with CMOS is that I'd like access to all those spare bits floating around! Very Happy Dirty R/2R networks take up even more board space, and cost nothing! Yeah!!

Aha! The truth comes out. Very Happy

That could also be done in a CPLD. Wink
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Uncle Krunkus
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PostPosted: Wed Oct 08, 2008 3:04 pm    Post subject: Reply with quote  Mark this post and the followings unread

I'm quite interested in the 40103, and I just need to get a few to start some experiments. I'm thinking of using those 8bits for the smallest divisor, and then using the carry out or precounting to add a bit or two as they are needed. That way, I would be squeezing the most functionality possible out of each chip.
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BOB-SNARE



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PostPosted: Wed Oct 08, 2008 6:10 pm    Post subject: Reply with quote  Mark this post and the followings unread

frijitz wrote:

In the tempered scale the ratio for a fifth is 2^(7/12) = 1.498. So at 1 kHz this would be 2 beats per second compared to the ratio of 1.5. Not too bad. But none of the other intervals are even that close.


Yep I know about Pythagorean tuning vs. Equal temperament. Very Happy

Based on the 9-bit values that were spec'd on page 1, there is a maximum of a 1-bit error, using 1.5x ratio on 5 lowest frequencies to give the the top 5 out of 12. (C-E to give G-B).
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urbanscallywag



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PostPosted: Mon Oct 13, 2008 6:23 pm    Post subject: Reply with quote  Mark this post and the followings unread

I didn't realize how few flip flops are in the smallest CPLD. I may have to eat my words about putting a top octave generator in such a small part. Embarassed

But I still think it can be done. Smile
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BOB-SNARE



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PostPosted: Mon Oct 13, 2008 6:36 pm    Post subject: Reply with quote  Mark this post and the followings unread

urbanscallywag wrote:
I didn't realize how few flip flops are in the smallest CPLD. I may have to eat my words about putting a top octave generator in such a small part. Embarassed

But I still think it can be done. Smile


Definitely Wink I can fit the 8-bit table into a 72 flip-flop version and it comes in a PLCC44 package (i.e. sockets have pins which are on a .1" grid, so definitely possible to veroboard).
I haven't tried the 9-bit table but I think I could get that into the 108 flip-flop (XC95108) CPLD (but the smallest package is PLCC84).
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urbanscallywag



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PostPosted: Mon Oct 13, 2008 6:37 pm    Post subject: Reply with quote  Mark this post and the followings unread

What are you using a table for?

And are you using VHDL, Verilog, or schematic capture?
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BOB-SNARE



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PostPosted: Mon Oct 13, 2008 7:00 pm    Post subject: Reply with quote  Mark this post and the followings unread

urbanscallywag wrote:
What are you using a table for?

By table, I meant the "magic" sequence that Scott posted before, not a LUT.

Quote:

And are you using VHDL, Verilog, or schematic capture?


VHDL
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urbanscallywag



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PostPosted: Mon Oct 13, 2008 10:21 pm    Post subject: Reply with quote  Mark this post and the followings unread

Cool.

9 flip flops for the main counter, and 13 flip flops for the outputs. 10 flip flops left.

Excuse me while I brush up on some fancy combinational logic...or switch to FPGA. Very Happy
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urbanscallywag



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PostPosted: Mon Oct 13, 2008 10:38 pm    Post subject: Reply with quote  Mark this post and the followings unread

I didn't know much about top octave synths before looking into them a little today, but it seems like other dividers are needed to generate 5 octaves of each of the 12 or 13 notes. These should probably be included in a CPLD/FPGA solution, right?

That way I could get away with using something bigger than the smallest CPLD Wink
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urbanscallywag



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PostPosted: Mon Oct 13, 2008 11:27 pm    Post subject: Reply with quote  Mark this post and the followings unread

I think the entire TOG + 13-5 octave dividers would fit into a $13 chip. It would require a small PCB to go along with it. Add in power regulation etc and this is getting expensive fast. Crying or Very sad

Sorry, I appear to have spoken before I knew enough about the problem earlier.
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